The present invention relates to manufacturing technologies for semiconductor devices and in particular to a technology effectively applicable to the reduction of chip cracking that occurs when a thinly formed semiconductor wafer is diced.
A structure for laminating multiple semiconductor elements stepwise over a wiring board has been disclosed (for example, Patent Document 1). In this structure, multiple semiconductor elements comprising a first element group are laminated stepwise over a wiring board; and multiple semiconductor elements comprising a second element group are laminated stepwise over the first element group in the opposite direction to the direction of the tiers in the first element group.
Another structure for laminating multiple semiconductor elements stepwise over a wiring board has been disclosed (for example, Patent Document 2). In this structure, multiple semiconductor elements comprising a first element group are laminated stepwise over a wiring board; multiple semiconductor elements comprising a second element group are laminated stepwise over the first element group in the opposite direction to the direction of the tiers in the first element group; and the semiconductor element in the lowermost tier in the second element group is laminated directly above the semiconductor element in the uppermost tier in the first element group with an insulating adhesive layer in between.
Another structure for laminating multiple semiconductor elements stepwise over a wiring board has been disclosed (for example, Patent Document 3). In this structure, multiple semiconductor elements comprising a first element group are laminated stepwise over a wiring board; multiple semiconductor elements comprising a second element group are laminated stepwise over the first element group in the opposite direction to the direction of the tiers in the first element group; and the semiconductor element positioned in the uppermost tier is thicker than the semiconductor elements positioned thereunder.    [Patent Document 1]    Japanese Unexamined Patent Publication No. 2009-88217    [Patent Document 2]    Japanese Unexamined Patent Publication No. 2009-158739    [Patent Document 3]    Japanese Unexamined Patent Publication No. 2009-176849